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Advancing Computer Architecture Research (ACAR)
ACAR II Report Now Complete
January 24, 2011 - The organizers of the ACAR visioning exercise have completed a report for the second workshop, this one titled Laying a New Foundation for IT: Computer Architecture for 2025 and Beyond. Please check it out!
Summary Slides Prepared
December 28, 2010 - The organizers have prepared slides summarizing the key findings from the two ACAR workshops. ] PDF | PPTx [
Report From the First ACAR Workshop Published
Sept. 20, 2010 -- The organizers of the ACAR visioning exercise have prepared a report following the first workshop, titled Failure is not an Option: Popular Parallel Programming. The report draws on the visions for basic research investment in parallel programming that emerged from the workshop. See more details below.
Discontinuity-inducing trends such as the arrival of multi/many-cores, the reduced reliability of semiconductors, and the ever-presence of power constraints, are transforming the field of computer architecture. Momentous changes are about to happen in all domains, including portable clients, home and business computing, and datacenter/petascale computing. In this environment, one asks:
- What will be the computing platforms in 2020-2025?
- What are the major architecture research challenges that must be overcome to create these platforms?
- What will be the impacts to and from the broader society at large?
To answer these questions, ACAR is organizing two workshops that, building on the 2005 CRA workshop on Revitalizing Computer Architecture Research, focus on what role computer architecture research plays going forward. The goals of these workshops are:
- Clearly articulate an agenda and roadmap for computer architecture research. Such an agenda must be broadly endorsed by the research and industrial communities as well as be an effective vehicle for communicating to technical and non-technical national leaders.
- Create excitement and community building for computer architecture research and form lasting research partnerships between multiple computer architecture researchers.
- Unlock the potential of the many junior researchers in our community and ensure the continuous leadership of our nation in this area.
- Suggest how to structure funding and research programs in a way that is commensurate with computer architecture's central role in computer science, the IT industry, and the US economy.
One of the two workshops will be on Popular Parallel Programming, while the other will be on Extending the Current Sequential Programming Model.
[Workshop]
What Now in Instruction-Level Parallelism Research
September 20-21, 2010, Seattle, WA
Historically, the computing industry has been driven by a set of exponential increases in singlethread performance. The ubiquity of multi-cores and the fact that much of the IT industry is relying on main-streaming parallel processing for survival is a truly seismic event. At the same time, there remains a huge gap between the theoretical limits of instruction-level parallelism (ILP) and what processors actually attain. Novel techniques to push ILP further in the familiar sequential execution model may yet to be invented. In this environment, one wonders if this is as good as it gets for ILP. Is ILP research over? Should it be? What are the truly new ideas and insights that can propel another three decades of exponential performance growth? How should ILP research be funded, performed and evaluated?
The wheels have come off the exponential track! - This Call for Position Papers is for the second of the two workshops and focuses on "Instruction Level Parallelism"; the first workshop focused on "Failure is Not an Option: Popular Parallel Programming". For this second workshop, members of the computer architecture community are invited to submit a 1-page position paper outlining their thoughts on ILP research. Some questions a submitter may wish to address are:
- Is there anything left to do with ILP research?
- Should funding agencies and industry support it?
- Should computer architecture conferences embrace it?
- What are the top 5 constraints on ILP in current microprocessors?
- What are the key new ideas and fruitful areas to explore in ILP?
- What is the role of re-configurability and heterogeneity in ILP?
- How to effectively support continuous run-time optimization in single-threaded systems?
Potential contributors are encouraged to be brief, and keep the following in mind:
- The position paper should not be about what you are working on currently; it should be about a vision for computer architectures available 10-15 years from now.
- There is no need to address all of the above questions. Addressing one or a few, or even others the submitter deems relevant is fine.
- Should computer architecture conferences embrace it?
- Keep the topic of ILP central.
- The steering committee will select the workshop invitees based on the responses. The committee is looking for a wide range of insightful, contrarian and forward thinking views.
Submit a 1-page PDF file to acar@cs.uiuc.edu by 6pm PST, August 6th, 2010.
Agenda:
Schedule [pdf]
CCC Council liaison for this effort:
Bill Feiereisen (Director of High Performance Computing, DoD for Lockheed Martin Corporation)
Organizers:
Mark Oskin (Univ. of Washingon) and Josep Torrellas (Univ. of Illinois)
Steering Committee:
Chita Das (NSF), Mark Hill (Univ. of Wisconsin), James Larus (Microsoft), Margaret Martonosi (Princeton), Jose Moreira (IBM), , Kunle Olukotun (Stanford), Mark Oskin (Univ. of Washington) and Josep Torrellas (Univ. of Illinois).
[Workshop (Invitation Only)]
Failure is not an Option: Popular Parallel Programming
February 22-23, 2010, San Diego, CA
The ubiquity of multi-cores and the fact that much of the IT industry is relying on main-streaming parallel processing for survival is a truly seismic event. Multi/many-cores will have to evolve to enable and support high-productivity parallel software development and execution.
Call for Position Papers [PDF | 16KB] (due November 30, 2009)
Issues and questions to be investigated
- How can computer architecture help enable ubiquitous parallel software development?
- How does the architecture most-effectively interact with the different layers of the software stack in parallel systems?
- What are the key parallel programming models requiring support; how to support multimodal parallelism?
- What is the role of re-configurability and heterogeneity in parallel systems: GPUs and other special-purpose parallel systems versus general-purpose parallel systems?
- How to effectively support continuous run-time optimization in parallel systems?
- What is the proper role of academic and state-sponsored research in parallel systems?
- How and whether to support parallel system building and prototyping efforts?
Leads for effort:
Josep Torrellas (Univ. of Illinois)
Mark Oskin (Univ. of Washington)
CCC Council liaison for this effort:
Bill Feiereisen (Director of High Performance Computing, DoD for Lockheed Martin Corporation)
Leads for this workshop:
Josep Torrellas (Univ. of Illinois)
Mark Oskin (Univ. of Washington)
CCC Council liaison for this Workshop:
Bill Feiereisen (Director of High Performance Computing, DoD for Lockheed Martin Corporation)
Agenda:
Complete Schedule [pdf]
Slides [pdf]:
Revolution on Demand: Push-button Specialized Supercomputers
Domain Specific Languages
Education
Funded Programs?
Industry Collaboration and the Parallelism Crisis
Data Center & Large-Scale Systems
Architectural Design for Enhancing Programmability
Participants
List of Attendees at the Workshop Wiki
Final Report
Final Report [pdf]
Workshop Wiki
http://iacoma.cs.uiuc.edu/acar1/
Blog Post
available soon
