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The last change was made on:
January 18, 2013.
Logistics:
Date: January 15 - 16, 2013
Location: Waterview Conference Center
Hotel: Le Méridien
We have set up a room block at the Le Méridien hotel, located next to the Waterview Conference Center. To make a reservation, please click here.
Travel & reimbursement:
The Computing Community Consortium (CCC) will cover travel expenses for all participants who desire it. Participants will be asked to make their own travel arrangements in advance, including purchasing airline tickets and making hotel reservations at the workshop hotel (see above). Following the symposium, CCC will circulate a reimbursement form that participants will need to complete and submit, along with copies of receipts for amounts exceeding $75.
In general, standard Federal travel policies apply: CCC will reimburse for non-refundable economy airfare on U.S. Flag carriers; and no alcohol will be covered.
For more information on Federal reimbursement guidelines, please follow the links below:
General Travel
International Travel
Additional questions about the reimbursement policy should be directed to Kenneth Hines, Program Associate, CCC (khines [at] cra.org).
Organizing Committee
Andrew Appel
Princeton University
Chris Daverse
Semiconductor Research Corporation
Kenneth Hines
Program Associate, Computing Community Consortium, Computing Research Association
Rafic Makki
GLOBALFOUNDRIES
Keith Marzullo
National Science Foundation
Celia Merzbacher
Semiconductor Research Corporation
Ron Perez
Advanced Micro Devices
Fred Schneider
Cornell
Mani Soma
University of Washington
Yervant Zorian
Synopsys
Resources
- Certification of software
- Semiconductor device fabrication
- Integrated circuit design
- Electronic design automation
- Hardware Trojans
- Lecture series on Hardware Oriented Security and Trust
- Online clearinghouse on secure/trustworthy hardware
Co-sponsored by:
Convergence of Software Assurance Methodologies and Trustworthy Semiconductor Design and Manufacture
Overview:
Ensuring that a computer chip or other semiconductor-based component does exactly what it the customer wants it to do, and nothing else, is becoming more challenging. Feature sizes continue to shrink and are measured in nanometers, circuits are more complex, and design and manufacture involves a supply chain typically comprising many businesses worldwide. Threats range from improper performance or early failure to allowing access to those with malicious intent.
Semiconductor design and manufacture depends on a "pipeline of tools," with each tool outputting something that is closer to describing what is actually produced and sold. One form of supply-chain attack involves corrupting one or more stages of this tools pipeline, so that the output of the pipeline exhibits undesirable functionality.
The programming languages community has, over the last two decades, addressed closely related problems with solutions such as "proof carrying code" and "certifying compilation" that derive from formal methods. Work in "compiler correctness" also is relevant. By analogy, semiconductor supply-chain attack might be frustrated if both the artifact and an analysis are transmitted between successive pipeline stages, with the analysis being updated by each stage. The updates would establish that properties checked by analysis in prior pipeline stages are preserved in the current pipeline stage. That is, each pipeline stage performs a kind of refinement, and checks that the refinement does not invalidate properties that previous stages validated. At the final stage, an accompanying analysis would rationalize the role of each element in the output of the pipeline.
This workshop is organized and sponsored by the Semiconductor Research Corporation (SRC), National Science Foundation (NSF), and Computing Community Consortium (CCC), will bring together academic and industry experts from both the programming language and semiconductor design/manufacture communities to share and discuss challenges to securing the semiconductor manufacturing process and strategies, based in part on experience in the programming language community, for addressing them.
Participation in the one-and-a-half day workshop is limited and by invitation only. The output will be a report outlining the problems and areas of research that have the potential to lead to solutions.
Agenda:
Day 1, January 15
| 7:30 am – 8:30 am | Continental breakfast |
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| 8:30 am -9:00 am | Welcome and Overview of the Workshop
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| 9:00 am -10:30 am |
Plenary Session 1: Overview of Semiconductor Design and Manufacture (with an eye toward the future)
Semiconductor Manufacture Tools & Processes and Potential Vulnerabilities (15 mins)— K. Kemp, Freescale Semiconductor Design Tools & Processes and Potential Vulnerabilities (15 mins)—S. Trimberger, Xilinx Top-to-bottom integrative design & verification (15 mins)—C. Seger, Intel Incorporation of designs from multiple sources (15 mins)—R. Aitken, ARM Panel Discussion (30 mins) |
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| 10:30 am -11:00 am |
Break |
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| 11:00 am -12:30 pm |
Plenary Session 2: Overview of Software Assurance Methodologies Moderator – Fred Schneider, Cornell Thinking about attacks / minimizing trusted base (20 mins)—A. Appel, Princeton CompCert as a software tool chain (20 minutes)—D. Pichardie, INRIA/Harvard Specifying the HW/SW interface (20 minutes)—P. Sewell, Cambridge Panel Discussion (30 mins) |
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| 12:30 pm -1:30 pm | Lunch |
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| 1:30 pm -5:00 pm | Breakout sessions |
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| 5:00 pm -6:00 pm | Preliminary Breakout reports (5 min each; bring forward one or two issues/ideas for consideration by all) |
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| 6:00 pm |
Reception |
Day 2, January 16
| 7:30 am - 8:30 am | Continental breakfast |
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| 8:30 am -8:35 am |
Welcome: Suzanne Iacono, Deputy Assistant Director, Directorate for Computer & Information Science & Engineer, NSF Opening remarks: Overview of Day 2 (Merzbacher/Epstein) |
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| 8:35 am -9:00 am |
Plenary session 3: Further food for thought Counterfeit chips: What are the threats? (20 mins + 5 mins Q&A)—M. Tehranipoor, U. Conn. |
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| 9:00 am -9:30 am | Why information flow is different from—and harder than—verifying other kinds of properties (20 mins + 5 mins Q&A)—S. Zdancewic, U. Penn. |
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| 9:30 am - 12:00 pm | Continue Breakout Groups to finalize output (with 15 min break) |
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| 12:00 pm -1:30 pm | Breakout Group reports & discussion—Working lunch |
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| 1:30 pm -2:00 pm | Wrap-up |
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| 2:00 pm | Adjourn |
