Extreme Scale Design Automation

Synopsis

Over a series of three workshops, participants will discuss a broad set of challenges facing the electronic design community, and how these challenges impact the design and fabrication of new electronic systems (both with conventional CMOS and with emerging technologies). The first workshop will focus on emerging technologies and the interplay between graduate education and the design automation workforce. The second workshop will focus on the challenges of system design with many billions of transistors. The final workshop will unify observations made into a series of milestones, benchmarks, and metrics, to help direct research efforts over the next decade.

Motivation and Overview

We have reached the point where semiconductor technology can no longer scale in the old ways (Dennard scaling) to pack new transistors in silicon chips. Research in design methods and manufacturing techniques of future electronic systems indicates that, in under ten years, computational systems will be fundamentally different from what they are today. To this end, the semiconductor industry has been involved in protracted roadmapping efforts (e.g. ITRS), but these efforts focused on the feasibility of production technologies (silicon and alternatives) and seek to minimize risk rather than maximize rewards. Industry roadmaps are unclear on how to move forward, and on how good the final result may be. To address this research vacuum, a significant investment has been placed in the development of new “emerging” fabrication technologies to augment or replace silicon devices. A large number of promising candidate technologies are now available, but require extensive ecosystems of computer-aided design tools, similar to those painstakingly developed for conventional technologies over the last 50 years. Even with conventional semiconductor technologies, existing electronic design automation (EDA) tools cannot effectively harness the scale possible in today’s chips.

To maintain continued leadership in technological innovation, despite adverse economic conditions, and to renovate national infrastructures for developing future electronic technologies, an investment is required in novel electronic design automation to facilitate the effective development of electronic systems of extreme scale integration complexity. In this vein, a series of workshops have been planned to consider carefully the broad range of possibilities currently available. Through an open discussion, workshop participants will develop a cohesive research strategy that can efficiently address the changing landscape for computing.

Workshop Goals:

The objective is to develop a consensus around the following questions

• What are most critical directions for EDA research in support of extreme scale designs?
  (e.g. validation,  power optimization and control, resilient and self-evolving systems design, technology- and application software-aware tools are clearly such challenges)
• What are potential new application domains for EDA? (computational biology, net-zero environmental impact systems, automotive?) Should EDA refocus on full systems?
• To what extent should EDA research agenda and funding be driven by the industry?
  (given that industry focuses on the near term and is highly cyclical)
• What are the best practices for collaboration between industry and academia?
  (considering the research and educational needs of the EDA community)
• What are the educational priorities for EDA?
  (from the workforce perspective and also with cutting-edge research in mind)

Workshop Scope

Each of the three workshops will address a portion of the computing landscape.

Workshop 1: Emerging Technologies and Workforce Continuity

Challenges for Emerging Technologies: there are a number of potentially disruptive ideas, which call for new device types, new interconnects and new ways to build chips to fundamentally alter the power, performance and cost profile of computing systems. Small examples of such chips, no matter how detailed, may not reliably establish the value of new techniques and risk to overlook significant pitfalls. On the other hand, working with full-sized systems that are not yet commercially viable is prohibitively expensive. This situation calls for relevant abstractions that allow researchers to address critical aspects of entire systems without having to spend resources on inconsequential details.

Ensuring the continuity of the workforce: The current state of affairs is aggravated by the dynamics of EDA education. We are confronted with a sagging interest by students in hardware design and particularly in electronic design automation. This is due in part to trendier specializations, such as social networking and machine learning, drawing students away from EDA jobs, as well as salary competition from companies rich with advertising revenue and high social appeal (e.g., Facebook and Google). Industry feedback indicates a shortage in qualified EDA professionals especially among fresh University graduates.  While these professionals are avid users of electronics that depend heavily on the development and use of sophisticated EDA tools for their design and validation, they feel much more removed from the potential impact they could have on people’s lives should they devote their careers to the EDA field.  While VLSI and architecture courses are an important part of the picture, the need for sophisticated EDA tools that can handle increased design complexity has been growing due to technology scaling, and will grow faster with the development of emerging technologies.  Two additional challenges are (1) to develop better EDA education materials, comparable to those currently available in VLSI design and computer architecture, and (2) to make the EDA career more attractive to students.

Workshop 2: Extreme-Scale Chips and Industry Research

The second workshop will be held in Austin, Texas, June 2-3, 2013.  The workshop will be co-located with the Design Automation Conference, and held in meeting rooms at the Austin convention center.

Challenges for Extreme-Scale Silicon Chips: individual devices may evolve from existing technologies, but the integration follows radically new scenarios and/or is super-optimized to achieve greater performance, lower power consumption, more tractable validation, etc. Again, small examples cannot always be sufficient for research on such systems, but full-sized systems are beyond the capabilities of most academic researchers. To faithfully represent realistic EDA challenges, public benchmarking infrastructure must be refreshed in sync with Moore’s law, tracking real designs. This has not been done in the past, but recent experience shows that abstracting particular challenges associated with scale enables powerful academic research helpful in designing next-generation systems.

Workshop 3: Achieving Sustainable Collaborations through Abstractions, Benchmarks, and Metrics

The third workshop will be held in San Jose, California, in November, co-located with the International Conference on Computer-Aided Design.  Logistics for this meeting will be available shortly.

The third workshop will focus on unifying the work of the prior two events, and developing a comprehensive set of abstractions, milestones, and metrics, to outline a path forward for design automation.  In particular, there will be an effort to develop a framework in which academia and industry can collaborate effectively.

In the past, EDA research has been driven by both academic and industry agendas. Industry representatives at SRC direct the flow of funding (some contributed by the NSF), but this funding has tended to target near-term problems specific to current industry needs. New models of collaboration with academia have been recently pioneered by IBM Research and Intel Labs, and our workshop will highlight such best practices where the industry actively works with the EDA community to formulate clean abstractions of key challenges, both near and far term, and follows up by providing independent evaluation of academic solutions.

Workshop Format and Anticipated Output:

Each of the workshops will feature keynote speakers to frame the key issues, followed by breakout group sessions in which participants will engage in open discussion.  Participants will have opportunities to present their views and observations.  Prior to each workshop, a set of survey questions will be provided, to further focus the discussions.

After each of the first two workshops, a summary of observations will be prepared by the workshop organizers.  A final report, unifying the work of all three workshops, will be prepared, approximately 6 weeks after the final meeting.