This summer I am working with the concept of Instruction Level Parallelism (ILP) through the use of register tiling. Many simulations performed by computers involve task graphs that calculate changes in data over time, with dependencies on previous data. By breaking up the graph into blocks (called register tiles) the programmer can use techniques that allow the compiler to better optimize code to allow for parallelism in the instruction pipeline. In other words, by using certain techniques with C code, when compiled the optimizations will allow for multiple instructions to be done at the same time (even when there are data dependencies).

I've finished the writeup for my first experiment. You can see it in pdf form here: Experimental Determination of ILP.

And here is the link to my lovely final paper: ILP and Register Tiling