| Project: |
Toward Better Memory Hierarchy for Chip-Multiprocessor |
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| Student Researchers: |
Lina Cordero, |
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| Advisor: |
Mohamed Zahran |
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| Institution: |
City College of City University of New York |
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| Webpage: |
http://ees2cy.engr.ccny.cuny.edu/www/web/mzahran/creu07/index.html |
With the tremendous enhancements done in process technology, having chip multiprocessor is nowadays the main architecture in use, as evidenced by the wide usage of Intel Core-duo (2 processors on chip). Also there are high end processors, such as SUN Ultrasparc Niagara that has 8 processors on chip. The number of cores per-chip is expected to double almost every two years. However, we cannot get the best performance from these cores, unless we have an efficient memory system, which is the main topic of this project. Memory is around 1000 times slower than the processor. Therefore, almost all the current processors have several caches organized as cache hierarchy, which are small, fast and expensive memory modules placed on-chip with the processors. With many on-chip processors, the design of this cache hierarchy becomes more challenging. The main question that this project tries to answer is: how will the cache hierarchy look like when the number of on-chip cores increases beyond 16 processors?